An engineering implementation guide for SoC designers integrating hardware-hardened post-quantum cryptographic accelerators into custom RISC-V silicon.
Open-standard RISC-V architectures are rapidly proliferating across aerospace, defense, and automotive microcontrollers. System designers require silicon-proven cryptographic IP blocks that seamlessly interface with standard on-chip buses (AHB, AXI4) while providing turnkey side-channel immunity.
Detailed bus interfacing: controlling the EmbeddedShield accelerator via memory-mapped AXI4-Lite registers while utilizing high-speed scatter-gather DMA engines to stream large polynomial vector matrices directly from system memory without CPU intervention.
Synthesis benchmarks across 12nm FinFET, 22nm FDX, and 28nm planar CMOS standard cell libraries, detailing gate counts (kGE), maximum clock frequencies, and static leakage optimization.