EmbeddedShield: 动态芯片金属屏蔽网、硬件级毛刺检测传感器与防物理拆解安全微控制器

EmbeddedShield Silicon Architecture & Side-Channel Masking Topology

Higher-order polynomial masking engine, dual-rail pre-charge logic, and optical fault sensor

Central System: Shielded Crypto Engine - Masked Lattice ALU

Cryptographic Nodes

• Random Mask Generator
• Masked NTT Multiplier
• Dual-Rail Asynchronous ALU
• Photodiode Glitch Sensor
• Clock Jitter Generator

Architectural Layers & Protocols

• Differential Logic Plane (Sense-Amplifier-Based Logic (SABL) / Dual-Rail): Ensuring identical power consumption for logic 0 and logic 1 transitions across all clock cycles.
• Algorithmic Polynomial Masking (First-Order and Second-Order Arithmetic Masking): Splitting lattice coefficients into random shares (x = x_A + x_B mod q) throughout NTT pipelines.
• Active Physical Fault Sensors (Substrate Light Diodes & Voltage Spike Detectors): Detecting laser fault injection (LFI) and power supply glitching during cryptographic execution.
• Execution Time Randomization (Randomized Shuffling & Dummy Instruction Insertion): Decorrelating electromagnetic radiation traces from algorithmic execution order.

Key Metrics: Order-2 (Higher-Order Masking Target) | > 5M Traces (DPA Resistance Threshold) | < 1.5 ns (Glitch Detection Latency) | Zero Branch (Fault-Resilient State Machine)